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Enhanced PWM (ePWM) Module
15.2.2.8.2 Controlling and Monitoring the Trip-Zone Submodule
The trip-zone submodule operation is controlled and monitored through the following registers:
Table 15-36. Trip-Zone Submodule Registers
Acronym Register Description Address Offset Shadowed
TZSEL Trip-Zone Select Register 24h No
TZCTL Trip-Zone Control Register 28h No
TZEINT Trip-Zone Enable Interrupt Register 2Ah No
TZFLG Trip-Zone Flag Register 2Ch No
TZCLR Trip-Zone Clear Register 2Eh No
TZFRC Trip-Zone Force Register 30h No
15.2.2.8.3 Operational Highlights for the Trip-Zone Submodule
The following sections describe the operational highlights and configuration options for the trip-zone
submodule.
The trip-zone signals at pin TZ1 to TZn is an active-low input signal. When the pin goes low, it indicates
that a trip event has occurred. Each ePWM module can be individually configured to ignore or use each of
the trip-zone pins. Which trip-zone pins are used by a particular ePWM module is determined by the
TZSEL register for that specific ePWM module. The trip-zone signal may or may not be synchronized to
the system clock (SYSCLKOUT). A minimum of 1 SYSCLKOUT low pulse on the TZ n inputs is sufficient
to trigger a fault condition in the ePWM module. The asynchronous trip makes sure that if clocks are
missing for any reason, the outputs can still be tripped by a valid event present on the TZn inputs.
The TZ n input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for a
ePWM module. The configuration is determined by the TZSEL[CBCn] and TZSEL[OSHTn] bits (where n
corresponds to the trip pin) respectively.
• Cycle-by-Cycle (CBC): When a cycle-by-cycle trip event occurs, the action specified in the TZCTL
register is carried out immediately on the EPWMxA and/or EPWMxB output. Table 15-37 lists the
possible actions. In addition, the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a
EPWMxTZINT interrupt is generated if it is enabled in the TZEINT register.
The specified condition on the pins is automatically cleared when the ePWM time-base counter
reaches zero (TBCNT = 0000h) if the trip event is no longer present. Therefore, in this mode, the trip
event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually
cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the
TZFLG[CBC] bit is cleared, then it will again be immediately set.
• One-Shot (OSHT): When a one-shot trip event occurs, the action specified in the TZCTL register is
carried out immediately on the EPWMxA and/or EPWMxB output. Table 15-37 lists the possible
actions. In addition, the one-shot trip event flag (TZFLG[OST]) is set and a EPWMxTZINT interrupt is
generated if it is enabled in the TZEINT register. The one-shot trip condition must be cleared manually
by writing to the TZCLR[OST] bit.
The action taken when a trip event occurs can be configured individually for each of the ePWM output
pins by way of the TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in
Table 15-37, can be taken on a trip event.
1543
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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