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CONTROL_MODULE Registers
Table 9-9. DDR PHY to IO Pin Mapping (continued)
Macro Pin CMD0 CMD1 CMD2 DATA0 DATA1
9 ddr_a9 ddr_casn Unconn ddr_dqs1 ddr_dqs0
10 ddr_a6 ddr_rasn Unconn ddr_dqsn1 ddr_dqsn0
9.3 CONTROL_MODULE Registers
Table 9-10 lists the memory-mapped registers for the CONTROL_MODULE. All other register offset
addresses not listed in Table 9-10 should be considered as reserved locations and the register contents
should not be modified.
Table 9-10. CONTROL_MODULE REGISTERS
Offset Acronym Register Description Section
0h control_revision Section 9.3.1
4h control_hwinfo Section 9.3.2
10h control_sysconfig Section 9.3.3
40h control_status Section 9.3.4
110h control_emif_sdram_config Section 9.3.5
41Ch cortex_vbbldo_ctrl Section 9.3.5
428h core_sldo_ctrl Section 9.3.6
42Ch mpu_sldo_ctrl Section 9.3.7
444h clk32kdivratio_ctrl Section 9.3.8
448h bandgap_ctrl Section 9.3.9
44Ch bandgap_trim Section 9.3.10
458h pll_clkinpulow_ctrl Section 9.3.11
468h mosc_ctrl Section 9.3.12
470h deepsleep_ctrl Section 9.3.13
50Ch dpll_pwr_sw_status Section 9.3.14
600h device_id Section 9.3.15
604h dev_feature Section 9.3.16
608h init_priority_0 Section 9.3.17
60Ch init_priority_1 Section 9.3.18
610h mmu_cfg Section 9.3.19
614h tptc_cfg Section 9.3.20
620h usb_ctrl0 Section 9.3.21
624h usb_sts0 Section 9.3.22
628h usb_ctrl1 Section 9.3.23
62Ch usb_sts1 Section 9.3.24
630h mac_id0_lo Section 9.3.25
634h mac_id0_hi Section 9.3.26
638h mac_id1_lo Section 9.3.27
63Ch mac_id1_hi Section 9.3.28
644h dcan_raminit Section 9.3.29
648h usb_wkup_ctrl Section 9.3.30
650h gmii_sel Section 9.3.31
664h pwmss_ctrl Section 9.3.32
670h mreqprio_0 Section 9.3.33
674h mreqprio_1 Section 9.3.34
690h hw_event_sel_grp1 Section 9.3.35
757
SPRUH73H–October 2011–Revised April 2013 Control Module
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