CONTROL_MODULE Registers
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Table 9-10. CONTROL_MODULE REGISTERS (continued)
Offset Acronym Register Description Section
694h hw_event_sel_grp2 Section 9.3.36
698h hw_event_sel_grp3 Section 9.3.37
69Ch hw_event_sel_grp4 Section 9.3.38
6A0h smrt_ctrl Section 9.3.39
6A4h mpuss_hw_debug_sel Section 9.3.40
6A8h mpuss_hw_dbg_info Section 9.3.41
770h vdd_mpu_opp_050 Section 9.3.42
774h vdd_mpu_opp_100 Section 9.3.43
778h vdd_mpu_opp_120 Section 9.3.44
77Ch vdd_mpu_opp_turbo Section 9.3.45
7B8h vdd_core_opp_050 Section 9.3.46
7BCh vdd_core_opp_100 Section 9.3.47
7D0h bb_scale Section 9.3.48
7F4h usb_vid_pid Section 9.3.49
7FCh efuse_sma Section 9.3.50
800h conf_gpmc_ad0 See the device datasheet for information on default pin Section 9.3.51
mux configurations. Note that the device ROM may
change the default pin mux for certain pins based on the
SYSBOOT mode settings.
804h conf_gpmc_ad1 Section 9.3.51
808h conf_gpmc_ad2 Section 9.3.51
80Ch conf_gpmc_ad3 Section 9.3.51
810h conf_gpmc_ad4 Section 9.3.51
814h conf_gpmc_ad5 Section 9.3.51
818h conf_gpmc_ad6 Section 9.3.51
81Ch conf_gpmc_ad7 Section 9.3.51
820h conf_gpmc_ad8 Section 9.3.51
824h conf_gpmc_ad9 Section 9.3.51
828h conf_gpmc_ad10 Section 9.3.51
82Ch conf_gpmc_ad11 Section 9.3.51
830h conf_gpmc_ad12 Section 9.3.51
834h conf_gpmc_ad13 Section 9.3.51
838h conf_gpmc_ad14 Section 9.3.51
83Ch conf_gpmc_ad15 Section 9.3.51
840h conf_gpmc_a0 Section 9.3.51
844h conf_gpmc_a1 Section 9.3.51
848h conf_gpmc_a2 Section 9.3.51
84Ch conf_gpmc_a3 Section 9.3.51
850h conf_gpmc_a4 Section 9.3.51
854h conf_gpmc_a5 Section 9.3.51
858h conf_gpmc_a6 Section 9.3.51
85Ch conf_gpmc_a7 Section 9.3.51
860h conf_gpmc_a8 Section 9.3.51
864h conf_gpmc_a9 Section 9.3.51
868h conf_gpmc_a10 Section 9.3.51
86Ch conf_gpmc_a11 Section 9.3.51
870h conf_gpmc_wait0 Section 9.3.51
874h conf_gpmc_wpn Section 9.3.51
758
Control Module SPRUH73H–October 2011–Revised April 2013
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