Texas Instruments AM335 Series Technical Reference Manual

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12.5.1.9 DMAENABLE_CLR Register (offset = 3Ch) [reset = 0h]
DMAENABLE_CLR is shown in Figure 12-13 and described in Table 12-13.
Per-Line DMA clr
Figure 12-13. DMAENABLE_CLR Register
31 30 29 28 27 26 25 24
Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved
R/W-0h
15 14 13 12 11 10 9 8
Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved Enable_1 Enable_0
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-13. DMAENABLE_CLR Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R/W 0h
1 Enable_1 R/W 0h Disable DMA request FIFO 1.
Write 0 = No action.
Read 0 = DMA line disabled.
Read 1 = DMA line enabled.
Write 1 = Disable DMA line.
0 Enable_0 R/W 0h Disable DMA request FIFO 0.
Write 0 = No action.
Read 0 = DMA line disabled.
Read 1 = DMA line enabled.
Write 1 = Disable DMA line.
1047
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English