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WATCHDOG
20.4.4.1.14 WDT_WIRQSTAT Register (offset = 58h) [reset = 0h]
WDT_WIRQSTAT is shown in Figure 20-112 and described in Table 20-125.
In the Watchdog Interrupt Status Register, IRQ masked status, status clear per-event enabled interrupt
status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after
interrupt has been serviced (raw status gets cleared, that is, even if not enabled).
Figure 20-112. WDT_WIRQSTAT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved EVENT_DLY EVENT_OVF
R-0h R/W1C-0h R/W1C-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-125. WDT_WIRQSTAT Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 EVENT_DLY R/W1C 0h
Clearable, enabled status for delay event
0x0x0(W) = No action
0x0x0(R) = No (enabled) event pending
0x0x1(W) = Clear (raw) event
0x0x1(R) = Event pending
0 EVENT_OVF R/W1C 0h
Clearable, enabled status for overflow event
0x0x0(W) = No action
0x0x0(R) = No (enabled) event pending
0x0x1(W) = Clear (raw) event
0x0x1(R) = Event pending
3695
SPRUH73H–October 2011–Revised April 2013 Timers
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