Enhanced PWM (ePWM) Module
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15.2.4.1.5 Time-Base Period Register (TBPRD)
The time-base period register (TBPRD) is shown in Figure 15-74 and described in Table 15-64.
Figure 15-74. Time-Base Period Register (TBPRD)
15 0
TBPRD
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 15-64. Time-Base Period Register (TBPRD) Field Descriptions
Bits Name Value Description
15-0 TBPRD 0-FFFFh These bits determine the period of the time-base counter. This sets the PWM frequency.
Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is
shadowed.
• If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the
shadow register. In this case, the active register will be loaded from the shadow register when the
time-base counter equals zero.
• If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active
register, that is the register actively controlling the hardware.
• The active and shadow registers share the same memory map address.
15.2.4.2 Counter-Compare Submodule Registers
Table 15-65 lists the memory-mapped registers for the counter-compare submodule. All other register
offset addresses not listed in Table 15-65 should be considered as reserved locations and the register
contents should not be modified.
Table 15-65. Counter-Compare Submodule Registers
Offset Acronym Register Description Section
Eh CMPCTL Counter-Compare Control Register Section 15.2.4.2.1
10h CMPAHR Counter-Compare A High-Resolution Register
(1)
Section 15.2.4.8.2
12h CMPA Counter-Compare A Register Section 15.2.4.2.2
14h CMPB Counter-Compare B Register Section 15.2.4.2.3
(1)
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved.
1586
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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