EDMA3 Registers
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11.4.1.8.2 QDMA Event Enable Register (QEER)
The EDMA3CC provides the option of selectively enabling/disabling each channel in the QDMA event
register (QER) by using the QDMA event enable register (QEER). If any of the event bits in QEER is set
(using the QDMA event enable set register, QEESR), it will enable that corresponding event. Alternatively,
if any event bit in QEER is cleared (using the QDMA event enable clear register, QEECR), it will disable
the corresponding QDMA channel. The QDMA event register will not latch any event for a QDMA channel,
if it is not enabled via QEER.
The QEER is shown in Figure 11-100 and described in Table 11-84.
Figure 11-100. QDMA Event Enable Register (QEER)
31 16
Reserved
R-0
15 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-84. QDMA Event Enable Register (QEER) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
7-0 En QDMA event enable for channels 0-7.
0 QDMA channel n is not enabled. QDMA event will not be recognized and will not latch in the QDMA
event register (QER).
1 QDMA channel n is enabled. QDMA events will be recognized and will get latched in the QDMA event
register (QER).
988
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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