GPMC
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7.1.5.14 GPMC_CONFIG4_i
WE# and OE# signals timing parameter configuration.
Figure 7-64. GPMC_CONFIG4_i
31 29 28 24
Reserved WEOFFTIME
R-0 R/W-0
23 22 20 19 16
WEEXTRADELAY Reserved WEONTIME
R/W-0 R-0 R/W-0
15 13 12 8
OEAADMUXOFFTIME OEOFFTIME
R/W-0 R/W-0
7 6 4 3 0
OEEXTRA OEAADMUXONTIME OEONTIME
DELAY
R/W-0 R/W-0 R/W-0
LEGEND: R = Read only; W1C = Write 1 to clear bit; -n = value after reset
Table 7-68. GPMC_CONFIG4_i Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reserved
28-24 WEOFFTIME WE# de-assertion time from start cycle time
0 0 GPMC_FCLK cycle
1h 1 GPMC_FCLK cycle
⋮ ⋮
1Fh 31 GPMC_FCLK cycles
23 WEEXTRADELAY WE# Add Extra Half GPMC.FCLK cycle
0 WE Timing control signal is not delayed
1 WE Timing control signal is delayed of half GPMC_FCLK clock cycle
22-20 Reserved 0 Reserved
19-16 WEONTIME WE# assertion time from start cycle time
0 0 GPMC_FCLK cycle
1h 1 GPMC_FCLK cycle
⋮ ⋮
Fh 15 GPMC_FCLK cycles
15-13 OEAADMUXOFFTIME OE# de-assertion time for the first address phase in an AAD-Multiplexed access
0 0 GPMC_FCLK cycle
1h 1 GPMC_FCLK cycle
⋮ ⋮
7h 7 GPMC_FCLK cycles
12-8 OEOFFTIME OE# de-assertion time from start cycle time
0 0 GPMC_FCLK cycle
1h 1 GPMC_FCLK cycle
⋮ ⋮
1Fh 31 GPMC_FCLK cycles
7 OEEXTRADELAY OE# Add Extra Half GPMC.FCLK cycle
0 OE Timing control signal is not delayed
1 OE Timing control signal is delayed of half GPMC_FCLK clock cycle
380
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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