www.ti.com
GPMC
Table 7-68. GPMC_CONFIG4_i Field Descriptions (continued)
Bit Field Value Description
6-4 OEAADMUXONTIME OE# assertion time for the first address phase in an AAD-Multiplexed access
0 0 GPMC_FCLK cycle
1h 1 GPMC_FCLK cycle
⋮ ⋮
7h 7 GPMC_FCLK cycles
3-0 OEONTIME OE# assertion time from start cycle time
0 0 GPMC_FCLK cycle
1h 1 GPMC_FCLK cycle
⋮ ⋮
Fh 15 GPMC_FCLK cycles
381
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated