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GPIO Registers
25.4.1.17 GPIO_DATAIN Register (offset = 138h) [reset = 0h]
GPIO_DATAIN is shown in Figure 25-23 and described in Table 25-22.
The GPIO_DATAIN register is used to register the data that is read from the GPIO pins. The
GPIO_DATAIN register is a read-only register. The input data is sampled synchronously with the interface
clock and then captured in the GPIO_DATAIN register synchronously with the interface clock. So, after
changing, GPIO pin levels are captured into this register after two interface clock cycles (the required
cycles to synchronize and to write the data). When the AUTOIDLE bit in the system configuration register
(GPIO_SYSCONFIG) is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the
data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command
has a 2 OCP cycle latency.
Figure 25-23. GPIO_DATAIN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-22. GPIO_DATAIN Register Field Descriptions
Bit Field Type Reset Description
31-0 DATAIN R 0h
Sampled Input Data
4085
SPRUH73H–October 2011–Revised April 2013 General-Purpose Input/Output
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