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7.3.5.4 SDRAM_CONFIG_2 Register (offset = Ch) [reset = 0h]
SDRAM_CONFIG_2 is shown in Figure 7-94 and described in Table 7-114.
Figure 7-94. SDRAM_CONFIG_2 Register
31 30 29 28 27 26 25 24
Reserved Reserved Reserved reg_ebank_pos Reserved
R-0h R/W-0h R-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved
R-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-114. SDRAM_CONFIG_2 Register Field Descriptions
Bit Field Type Reset Description
31 Reserved R 0h
30 Reserved R/W 0h
Reserved.
29-28 Reserved R 0h
27 reg_ebank_pos R/W 0h External bank position.
Set to 0 to assign external bank address bits from lower OCP
address, as shown in the tables for OCP Address to DDR2/3/mDDR
Address Mapping.
Set to 1 to assign external bank address bits from higher OCP
address bits, as shown in the tables for OCP Address to
DDR2/3/mDDR Address Mapping.
26-6 Reserved R 0h
5-4 Reserved R/W 0h
Reserved.
3 Reserved R 0h
2-0 Reserved R/W 0h
Reserved.
428
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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