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GPIO Registers
25.4.1.19 GPIO_LEVELDETECT0 Register (offset = 140h) [reset = 0h]
GPIO_LEVELDETECT0 is shown in Figure 25-25 and described in Table 25-24.
The GPIO_LEVELDETECT0 register is used to enable/disable for each input lines the low-level (0)
detection to be used for the interrupt request generation. Enabling at the same time high-level detection
and low-level detection for one given pin makes a constant interrupt generator.
Figure 25-25. GPIO_LEVELDETECT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEVELDETECT0[n]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-24. GPIO_LEVELDETECT0 Register Field Descriptions
Bit Field Type Reset Description
31-0 LEVELDETECT0[n] R/W 0h
Low Level Interrupt Enable
0x0 = Disable the IRQ assertion on low-level detect.
0x1 = Enable the IRQ assertion on low-level detect.
4087
SPRUH73H–October 2011–Revised April 2013 General-Purpose Input/Output
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