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CONTROL_MODULE Registers
9.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h]
mreqprio_0 is shown in Figure 9-36 and described in Table 9-43.
Figure 9-36. mreqprio_0 Register
31 30 29 28 27 26 25 24
Reserved sgx Reserved usb1
R-0h R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved usb0 Reserved cpsw
R-0h R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved Reserved Reserved pru_icss_pru0
R-0h R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved sab_init1 Reserved sab_init0
R-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-43. mreqprio_0 Register Field Descriptions
Bit Field Type Reset Description
31 Reserved R 0h
30-28 sgx R/W 0h MReqPriority for SGX Initiator OCP Interface
27 Reserved R 0h
26-24 usb1 R/W 0h MReqPriority for USB1 Initiator OCP Interface
23 Reserved R 0h
22-20 usb0 R/W 0h MReqPriority for USB0 Initiator OCP Interface
19 Reserved R 0h
18-16 cpsw R/W 0h MReqPriority for CPSW Initiator OCP Interface
15 Reserved R 0h
14-12 Reserved R 0h
11 Reserved R 0h
10-8 pru_icss_pru0 R/W 0h MReqPriority for PRU-ICSS PRU0 Initiator OCP Interface
7 Reserved R 0h
6-4 sab_init1 R/W 0h MReqPriority for MPU Initiator 1 OCP Interface
3 Reserved R 0h
2-0 sab_init0 R/W 0h MReqPriority for MPU Initiator 0 OCP Interface
797
SPRUH73H–October 2011–Revised April 2013 Control Module
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