Functional Description
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Where the frequency is the CLK frequency.
14.3.2.4.5 Command IDLE
The cmd_idle bit in the DMA_Control register allows CPDMA operation to be suspended. When the idle
state is commanded, the CPDMA will stop processing receive and transmit frames at the next frame
boundary. Any frame currently in reception or transmission will be completed normally without suspension.
For transmission, any complete or partial frame in the tx cell fifo will be transmitted. For receive, frames
that are detected by the CPDMA after the suspend state is entered are ignored. No statistics will be kept
for ignored frames. Commanded idle is similar in operation to emulation control and clock stop.
14.3.2.5 VLAN Aware Mode
The CPSW_3G is in VLAN aware mode when the CPSW Control register vlan_aware bit is set. In VLAN
aware mode ports 0 receive packets (out of the CPSW_3G) may or may not be VLAN encapsulated
depending on the CPSW Control register rx_vlan_encap bit. The header packet VLAN is generated as
described in Section 14.3.3, Ethernet Mac Sliver (CPGMAC_SL). Port 0 receive packet data is never
modified. VLAN is not removed regardless of the force untagged egress bit for Port 0. VLAN encapsulated
receive packets have a 32-bit VLAN header encapsulation word added to the packet data.VLAN
encapsulated packets are specified by a set rx_vlan_encap bit in the packet buffer descriptor.
Port 0 transmit packets are never VLAN encapsulated (encapsulation is not allowed).
In VLAN aware mode, transmitted packet data is changed depending on the packet type (pkt_type),
packet priority (pkt_pri), and VLAN information as shown in the below tables:
Figure 14-9. VLAN Header Encapsulation Word
31 29 28 27 16
HDR_PKT_Priority HDR_PKT_CFI HDR_PKT_Vid
15 10 9 8 7 6 5 4 3 2 1 0
Reserved PKT_Type Reserved
Table 14-9. VLAN Header Encapsulation Word Field Descriptions
Field Description
HDR_PKT_Priority Header Packet VLAN priority (Highest priority: 7)
HDR_PKT_CFI Header Packet VLAN CFI bit.
HDR_PKT_Vid Header Packet VLAN ID
Packet Type. Indicates whether the packet is VLAN-tagged, priority-tagged, or non-tagged.
00: VLAN-tagged packet
PKT_Type 01: Reserved
10: Priority-tagged packet
11: Non-tagged packet
14.3.2.6 VLAN Unaware Mode
The CPSW_3G is in VLAN unaware mode when the CPSW Control register vlan_aware bit is cleared.
Port 0 receive packets (out of the CPSW_3G) may or may not be VLAN encapsulated depending on the
CPSW Control register rx_vlan_encap bit. Port 0 transmit packets are never VLAN encapsulated.
14.3.2.7 Address Lookup Engine (ALE)
The address lookup engine (ALE) processes all received packets to determine which port(s) if any that the
packet should the forwarded to. The ALE uses the incoming packet received port number, destination
address, source address, length/type, and VLAN information to determine how the packet should be
forwarded. The ALE outputs the port mask to the switch fabric that indicates the port(s) the packet should
be forwarded to. The ALE is enabled when the ale_enable bit in the ALE_Control register is set. All
packets are dropped when the ale_enable bit is cleared to zero.
1194
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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