I2C Registers
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21.4.1.20 I2C_OA Register (offset = A8h) [reset = 0h]
I2C_OA is shown in Figure 21-35 and described in Table 21-28.
CAUTION: During an active transfer phase (between STT having been set to 1 and reception of ARDY),
no modification must be done in this register. Changing it may result in an unpredictable behavior. This
register is used to specify the module s base I2C 7-bit or 10-bit address (base own address).
Figure 21-35. I2C_OA Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved OA
R-0h R/W-0h
7 6 5 4 3 2 1 0
OA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-28. I2C_OA Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9-0 OA R/W 0h Own address.
This field specifies either: A
10-bit address coded on OA
[9:0] when XOA (Expand Own Address, I2C_CON[7]) is set to 1.
or A
7-bit address coded on OA
[6:0] when XOA (Expand Own Address, I2C_CON[7]) is cleared to 0.
In this case, OA
[9:7] bits must be cleared to 000 by application software.
Value after reset is low (all 10 bits).
3752
I2C SPRUH73H–October 2011–Revised April 2013
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