Functional Description
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16.3.9.6.1.2 CPPI DMA Scheduler Programming Examples
Consider a three endpoints use on a system with the following configurations: EP1-Tx, EP2-Rx, and EP2-
Tx. Two assumptions are considered:
Case 1: Assume that you would like to service each enabled endpoints (EP1-Tx, EP2-Rx, and EP2-Tx)
with equal priority.
The scheduler handles the rate at which an endpoint is serviced by the number of credits programmed
(entries) for that particular endpoint within the scheduler Table Words. The scheduler has up to 256
credits that it can grant and for this example the user can configure the number of entries/credits to be
anywhere from 3 to 256 with a set of 3 entries.
However, the optimum and direct programming for this scenario would be programming only the first three
entries of the scheduler via scheduler Table WORD[0]. Since this case expects the Scheduler to use only
the first three entries, you communicate that by programming DMA_SCHED_CTRL.LAST_ENTRY with 2
(that is, 3 -1). The Enabled Endpoint numbers and the data transfer direction is then communicated by
programming the first three entries of WORD[0] (ENTRY0_CHANNEL = 1: ENTRY0_RXTX = 0;
ENTRY1_CHANNEL = 2: ENTRY1_RXTX = 1;ENTRY2_CHANNEL = 2: ENTRY2_RXTX = 0). With this
programming, the Scheduler will only service the first three entries in a round-robin fashion, checking each
credited endpoint for transfer one after the other, and servicing the endpoint that has data to transfer.
Case 2: Enabled endpoint EP1-Tx is serviced at twice the rate as the other enabled endpoints (EP2-Rx
and EP2-Tx).
The number of entries/credit that has to be awarded to EP1-Tx has to be twice as much of the others.
Four entries/credits would suffix to satisfy our requirement with two credits for EP1-Tx, one credit for EP2-
Rx, and one credit for EP2-Tx. This requirement is satisfied by allocating any two of the four entries to
EP1-Tx endpoint. Again for this example, scheduler Table WORD[0] would suffice since it can handle the
first 4 entries. Even though several scenarios exist to programming the order of service for this case, one
scenario would be to allow servicing EP1-Tx to back-to-back followed by the other enabled endpoints.
Program DMA_SCHED_CTRL.LAST_ENTRY with 3 (that is, 4 -1). Program WORD[0]
(ENTRY0_CHANNEL = 1: ENTRY0_RXTX = 0; ENTRY1_CHANNEL = 1: ENTRY1_RXTX = 0;
ENTRY2_CHANNEL = 2: ENTRY2_RXTX = 1; ENTRY3_CHANNEL = 2: ENTRY3_RXTX = 0).
16.3.9.7 CPPI DMA State Registers
The port must store and maintain state information for each transmit and receive port/channel. The state
information is referred to as the Tx DMA State and Rx DMA State.
16.3.9.7.1 Transmit DMA State Registers
The Tx DMA State is a combination of control fields and protocol specific port scratchpad space used to
manipulate data structures and transmit packets. Each transmit channel has two queues. Each queue has
a one head descriptor pointer and one completion pointer. There are thirty Tx DMA State registers; one for
each port/channel.
The following information is stored in the Tx DMA State:
• Tx Queue Head Descriptor Pointer(s)
• Tx Completion Pointer(s)
• Protocol specific control/status (port scratchpad)
16.3.9.7.2 Receive DMA State Registers
The Rx DMA State is a combination of control fields and protocol specific port scratchpad space used to
manipulate data structures in order to receive packets. Each receive channel has only one queue. Each
channel queue has one head descriptor pointer and one completion pointer. There are thirty Rx DMA
State registers; one for each port/channel.
The following information is stored in the Rx DMA State:
• Rx Queue Head Descriptor Pointer
• Rx Queue Completion Pointer
1748
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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