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GPMC
7.1.4.1.4 GPMC Configuration for Asynchronous Read Access
The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns).
Table 7-48 shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
Table 7-49 shows how to calculate timings for the GPMC using the memory parameters.
Figure 7-49 shows the asynchronous read access.
Table 7-48. AC Characteristics for Asynchronous Read Access
AC Read Characteristics
Description Duration (ns)
on the Memory Side
tCE Read Access time from CSn low 80
tAAVDS Address setup time to rising edge of ADVn 3
tAVDP ADVn low time 6
tCAS CSn setup time to ADVn 0
tOE Output enable to output valid 6
tOEZ Output enable to High-Impedance 7
Use the following formula to calculate the RdCycleTime parameter for this typical access:
RdCycleTime = RdAccessTime + AccessCompletion = RdAccessTime + 1 clock cycle + tOEZ
• First, on the memory side, the external memory makes the data available to the output bus. This is the
memory-side read access time defined in Table 7-49: the number of clock cycles between the address
capture (ADVn rising edge) and the data valid on the output bus.
The GPMC requires some hold time to allow the data to be captured correctly and the access to be
finished.
• To read the data correctly, the GPMC must be configure to meet the data setup time requirement of
the memory; the GPMC module captures the data on the next rising edge. This is access time on the
GPMC side.
• There must also be a data hold time for correctly reading the data (checking that there is no OEn/CSn
deassertion while reading the data). This data hold time is 1 clock cycle (that is, AccessTime + 1).
• To complete the access, OEn/CSn signals are driven to high-impedance. AccessTime + 1 + tOEZ is
the read cycle time.
• Addresses can now be relatched and a new read cycle begun.
359
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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