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WATCHDOG
20.4.4.1.6 WDT_WCLR Register (offset = 24h) [reset = 20h]
WDT_WCLR is shown in Figure 20-104 and described in Table 20-117.
The Watchdog Control Register controls the prescaler stage of the counter.
Figure 20-104. WDT_WCLR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PRE PTV Reserved
R-0h R/W-1h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-117. WDT_WCLR Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5 PRE R/W 1h
Prescaler enable/disable configuration
0x0 = Prescaler disabled
0x1 = Prescaler enabled
4-2 PTV R/W 0h Prescaler value.
The timer counter is prescaled with the value: 2**PTV.
Example: PTV = 3 then counter increases value if started after 8
functional clock periods.
On reset, it is loaded from PI_PTV_RESET_VALUE input port.
1-0 Reserved R 0h
3687
SPRUH73H–October 2011–Revised April 2013 Timers
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