Ethernet Subsystem Registers
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14.5.1.7 TBLW1 Register (offset = 38h) [reset = 0h]
TBLW1 is shown in Figure 14-21 and described in Table 14-31.
ADDRESS LOOKUP ENGINE TABLE WORD 1 REGISTER
Figure 14-21. TBLW1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENTRY63_32
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-31. TBLW1 Register Field Descriptions
Bit Field Type Reset Description
31-0 ENTRY63_32 R/W 0h Table entry bits
63:32
1248
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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