Power, Reset, and Clock Management
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8.1.12.1.4 CM_PER_L3_CLKSTCTRL Register (offset = Ch) [reset = 12h]
CM_PER_L3_CLKSTCTRL is shown in Figure 8-26 and described in Table 8-33.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-26. CM_PER_L3_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CLKACTIVITY_MCAS CLKACTIVITY_CPTS Reserved CLKACTIVITY_L3_G CLKACTIVITY_MMC_ CLKACTIVITY_EMIF_ CLKTRCTRL
P_GCLK _RFT_GCLK CLK FCLK GCLK
R-0h R-0h R-0h R-1h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-33. CM_PER_L3_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7 CLKACTIVITY_MCASP_ R 0h
This field indicates the state of the MCASP_GCLK clock in the
GCLK
domain.
0x0 = Inact
0x1 = Act
6 CLKACTIVITY_CPTS_RF R 0h
This field indicates the state of the
T_GCLK
CLKACTIVITY_CPTS_RFT_GCLK clock in the domain.
0x0 = Inact
0x1 = Act
5 Reserved R 0h
4 CLKACTIVITY_L3_GCLK R 1h
This field indicates the state of the L3_GCLK clock in the domain.
0x0 = Inact
0x1 = Act
3 CLKACTIVITY_MMC_FCL R 0h
This field indicates the state of the MMC_GCLK clock in the domain.
K
0x0 = Inact
0x1 = Act
2 CLKACTIVITY_EMIF_GC R 0h
This field indicates the state of the EMIF_GCLK clock in the domain.
LK
0x0 = Inact
0x1 = Act
1-0 CLKTRCTRL R/W 2h
Controls the clock state transition of the L3 clock domain.
0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated.
Wakeup transition may however occur.
0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep
transition on the domain.
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up
transition on the domain.
0x3 = Reserved : Reserved.
554
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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