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McASP Registers
22.4.1.21 Receiver Status Register (RSTAT)
The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If
the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear
it, the McASP logic has priority and the flag remains set. This also causes a new interrupt request to be
generated. The RSTAT is shown in Figure 22-59 and described in Table 22-32.
Figure 22-59. Receiver Status Register (RSTAT)
31 9 8
Reserved RERR
R-0 R/W-0
7 6 5 4 3 2 1 0
RDMAERR RSTAFRM RDATA RLAST RTDMSLOT RCKFAIL RSYNCERR ROVRN
R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R-0 R/W1C-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Writing a 1 clears this bit; writing a 0 has no effect.; -n = value after reset
Table 22-32. Receiver Status Register (RSTAT) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
8 RERR RERR bit always returns a logic-OR of:ROVRN | RSYNCERR | RCKFAIL | RDMAERR
Allows a single bit to be checked to determine if a receiver error interrupt has occurred.
0 No errors have occurred.
1 An error has occurred.
7 RDMAERR Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the
data port in a given time slot than were programmed as receivers. Causes a receive interrupt (RINT), if
this bit is set and RDMAERR in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0
to this bit has no effect.
0 Receive DMA error did not occur.
1 Receive DMA error did occur.
6 RSTAFRM Receive start of frame flag. Causes a receive interrupt (RINT), if this bit is set and RSTAFRM in
RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.
0 No new receive frame sync (AFSR) is detected.
1 A new receive frame sync (AFSR) is detected.
5 RDATA Receive data ready flag. Causes a receive interrupt (RINT), if this bit is set and RDATA in RINTCTL is
set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.
0 No new data in RBUF.
1 Data is transferred from XRSR to RBUF and ready to be serviced by the CPU or DMA. When RDATA is
set, it always causes a DMA event (AREVT).
4 RLAST Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame.
Causes a receive interrupt (RINT), if this bit is set and RLAST in RINTCTL is set. This bit is cleared by
writing a 1 to this bit. Writing a 0 to this bit has no effect.
0 Current slot is not the last slot in a frame.
1 Current slot is the last slot in a frame. RDATA is also set.
3 RTDMSLOT Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time
slot is even or odd.
0 Current TDM time slot is odd.
1 Current TDM time slot is even.
2 RCKFAIL Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an
error (see Clock Failure Detection). Causes a receive interrupt (RINT), if this bit is set and RCKFAIL in
RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.
0 Receive clock failure did not occur.
1 Receive clock failure did occur.
3857
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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