Power, Reset, and Clock Management
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8.1.13.2.1 RM_PER_RSTCTRL Register (offset = 0h) [reset = 2h]
RM_PER_RSTCTRL is shown in Figure 8-169 and described in Table 8-185.
This register controls the release of the PER Domain resets.
Figure 8-169. RM_PER_RSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved PRU_ICSS_LRST Reserved
R-0h R-0h R-0h R/W-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-185. RM_PER_RSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5-3 Reserved R 0h
2 Reserved R 0h
1 PRU_ICSS_LRST R/W 1h
PER domain PRU-ICSS local reset control
0x0 = CLEAR : Reset is cleared for the PRU-ICSS
0x1 = ASSERT : Reset is asserted for the PRU-ICSS
0 Reserved R 0h
712
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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