www.ti.com
EMIF
7.3.5.28 IRQENABLE_CLR_SYS Register (offset = BCh) [reset = 0h]
IRQENABLE_CLR_SYS is shown in Figure 7-118 and described in Table 7-138.
Figure 7-118. IRQENABLE_CLR_SYS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved reg_en_ta_sys reg_en_err_sys
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-138. IRQENABLE_CLR_SYS Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 Reserved R/W 0h
Reserved.
1 reg_en_ta_sys R/W 0h Enable clear for system OCP interrupt.
Writing a 1 will disable the interrupt, and clear this bit as well as the
corresponding Interrupt Enable Set Register.
Writing a 0 has no effect.
0 reg_en_err_sys R/W 0h Enable clear for system OCP interrupt.
Writing a 1 will disable the interrupt, and clear this bit as well as the
corresponding Interrupt Enable Set Register.
Writing a 0 has no effect.
453
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
