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Ethernet Subsystem Registers
14.5.10.13 MDIO User Access Register 1 (MDIOUSERACCESS1)
The MDIO user access register 1 (MDIOUSERACCESS1) is shown in Figure 14-244 and described in
Table 14-263.
Figure 14-244. MDIO User Access Register 1 (MDIOUSERACCESS1)
31 30 29 28 26 25 21 20 16
GO WRITE ACK Reserved REGADR PHYADR
R/W/S-0 R/W-0x0 R/W-0x0 R-0x0 R/W-0x0 R/W-0x0
15 0
DATA
R/W-0x0
LEGEND: R/W = Read/Write; R = Read only; S = Status; -n = value after reset
Table 14-263. MDIO User Access Register 1 (MDIOUSERACCESS1) Field Descriptions
Bit Field Value Description
31 GO 0-1 Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it
is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit
has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will
self clear when the requested access has been completed. Any writes to the
MDIOUSERACCESS0 register are blocked when the GO bit is 1. If byte access is being
used, the GO bit should be written last.
30 WRITE 0-1 Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write,
otherwise it is a register read.
29 ACK 0-1 Acknowledge. This bit is set if the PHY acknowledged the read transaction.
28-26 Reserved 0 Reserved.
25-21 REGADR 0-1Fh Register address; specifies the PHY register to be accessed for this transaction.
20-16 PHYADR 0-1Fh PHY address; specifies the PHY to be accesses for this transaction.
15-0 DATA 0-FFFFh User data. The data value read from or to be written to the specified PHY register.
1483
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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