WATCHDOG
www.ti.com
20.4.4.1.3 WDT_WDST Register (offset = 14h) [reset = 1h]
WDT_WDST is shown in Figure 20-101 and described in Table 20-114.
The Watchdog Status Register provides status information about the module.
Figure 20-101. WDT_WDST Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved RESETDONE
R-0h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-114. WDT_WDST Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 RESETDONE R 1h
Internal module reset monitoring
0x0 = Internal module reset is ongoing.
0x1 = Reset completed
3684
Timers SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
