Texas Instruments AM335 Series Technical Reference Manual

Control Module
TSC_ADC Subsystem
TIMER7
ADV_EVTCAPT[3:0]
ext_hw_event
MPU Subsystem,
PRU-ICSS,
WakeM3
AFE
Sequencer
FSM
SCR
M
IPG
FIFO0
64x16-bit
FIFO1
64x16-bit
S
S
ADC
M
S
0
1
2
3
4
L3Slow
Interconnect
L4Wakeup
Interconnect
gen_intr
fifo0_dreq
fifo1_dreq
EDMA
AN[7:0]
TSC_ADC
Pads
TIMER6
TIMER5
TIMER4
pointr_pend
PRU-ICSS
pr1_host_intr0
pointr_pend
pointr_pend
pointr_pend
pd_wkup_adc_fclk
CLK_M_OSC
PRCM
adc_clk
ADC_EVT_CAPT
DMA
SLV
OCP2VBUS
Bridge
MMA
SLV
OCP2VBUS
Bridge
Integration www.ti.com
12.2 Integration
Figure 12-1 shows the integration of the TSC_ADC module in the device.
Figure 12-1. TSC_ADC Integration
pr1_host_intr[0:7] corresponds to Host-2 to Host-9 of the PRU-ICSS interrupt controller.
12.2.1 TSC_ADC Connectivity Attributes
The general connectivity attributes for the TSC_ADC module are summarized in Table 12-1.
Table 12-1. TSC_ADC Connectivity Attributes
Attributes Type
Power domain Wakeup Domain
Clock domain PD_WKUP_L4_WKUP_GCLK (OCP)
PD_WKUP_ADC_FCLK (Func)
Reset signals WKUP_DOM_RST_N
Idle/Wakeup signals Smart idle
Wakeup
Interrupt request 1 interrupt to MPU Subsystem (ADC_TSC_GENINT), PRU-ICSS
(gen_intr_pend), and WakeM3
DMA request 2 Events (tsc_adc_FIFO0, tsc_adc_FIFO1)
Physical address L3 Slow slave port (DMA)
L4 Wkup slave port (MMR)
1024
Touchscreen Controller SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English