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McASP Registers
22.4.1.17 Receive Clock Control Register (ACLKRCTL)
The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive
clock generator. The ACLKRCTL is shown in Figure 22-55 and described in Table 22-28.
Figure 22-55. Receive Clock Control Register (ACLKRCTL)
31 16
Reserved
R-0
15 8 7 6 5 4 0
Reserved CLKRP Rsvd CLKRM CLKRDIV
R-0 R/W-0 R-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-28. Receive Clock Control Register (ACLKRCTL) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
7 CLKRP Receive bitstream clock polarity select bit.
0 Falling edge. Receiver samples data on the falling edge of the serial clock, so the external transmitter
driving this receiver must shift data out on the rising edge of the serial clock.
1 Rising edge. Receiver samples data on the rising edge of the serial clock, so the external transmitter
driving this receiver must shift data out on the falling edge of the serial clock.
6 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
5 CLKRM Receive bit clock source bit. Note that this bit does not have any effect, if ACLKXCTL.ASYNC = 0.
0 External receive clock source from ACLKR pin.
1 Internal receive clock source from output of programmable bit clock divider.
4-0 CLKRDIV 0-1Fh Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that
this bit does not have any effect, if ACLKXCTL.ASYNC = 0.
0 Divide-by-1.
1h Divide-by-2.
2h-1Fh Divide-by-3 to divide-by-32.
3853
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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