I2C Registers
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21.4.1.14 I2C_DMATXWAKE_EN Register (offset = 4Ch) [reset = 0h]
I2C_DMATXWAKE_EN is shown in Figure 21-29 and described in Table 21-22.
All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup
(on the appropriate swakeup line). Note that the I2C_SYSC.ENAWAKEUP field is the global (slave)
wakeup enabler, and that it is disabled by default.
Figure 21-29. I2C_DMATXWAKE_EN Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved XDR RDR Reserved ROVR XUDF AAS BF
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved STC GC Reserved DRDY ARDY NACK AL
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-22. I2C_DMATXWAKE_EN Register Field Descriptions
Bit Field Type Reset Description
31-15 Reserved R 0h
14 XDR R/W 0h
Transmit draining wakeup set.
0x0 = Transmit draining interrupt disabled
0x1 = Transmit draining interrupt enabled
13 RDR R/W 0h
Receive draining wakeup set.
0x0 = Receive draining interrupt disabled
0x1 = Receive draining interrupt enabled
12 Reserved R 0h
11 ROVR R/W 0h
Receive overrun wakeup set.
0x0 = Receive overrun interrupt disabled
0x1 = Receive draining interrupt enabled
10 XUDF R/W 0h
Transmit underflow wakeup set.
0x0 = Transmit underflow interrupt disabled
0x1 = Transmit underflow interrupt enabled
9 AAS R/W 0h
Address as slave IRQ wakeup set.
0x0 = Addressed as slave interrupt disabled
0x1 = Addressed as slave interrupt enabled
8 BF R/W 0h
Bus free IRQ wakeup set.
0x0 = Bus free wakeup disabled
0x1 = Bus free wakeup enabled
7 Reserved R 0h
6 STC R/W 0h
Start condition IRQ wakeup set.
0x0 = Start condition wakeup disabled
0x1 = Start condition wakeup enabled
5 GC R/W 0h
General call IRQ wakeup set.
0x0 = General call wakeup disabled
0x1 = General call wakeup enabled
3742
I2C SPRUH73H–October 2011–Revised April 2013
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