Texas Instruments AM335 Series Technical Reference Manual

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22.4.1.20 Receiver Interrupt Control Register (RINTCTL)
The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt
(RINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates
RINT. The RINTCTL is shown in Figure 22-58 and described in Table 22-31. See Section 22.4.1.21 for a
description of the interrupt conditions.
Figure 22-58. Receiver Interrupt Control Register (RINTCTL)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
RSTAFRM Reserved RDATA RLAST RDMAERR RCKFAIL RSYNCERR ROVRN
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-31. Receiver Interrupt Control Register (RINTCTL) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
7 RSTAFRM Receive start of frame interrupt enable bit.
0 Interrupt is disabled. A receive start of frame interrupt does not generate a McASP receive interrupt
(RINT).
1 Interrupt is enabled. A receive start of frame interrupt generates a McASP receive interrupt (RINT).
6 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
5 RDATA Receive data ready interrupt enable bit.
0 Interrupt is disabled. A receive data ready interrupt does not generate a McASP receive interrupt
(RINT).
1 Interrupt is enabled. A receive data ready interrupt generates a McASP receive interrupt (RINT).
4 RLAST Receive last slot interrupt enable bit.
0 Interrupt is disabled. A receive last slot interrupt does not generate a McASP receive interrupt (RINT).
1 Interrupt is enabled. A receive last slot interrupt generates a McASP receive interrupt (RINT).
3 RDMAERR Receive DMA error interrupt enable bit.
0 Interrupt is disabled. A receive DMA error interrupt does not generate a McASP receive interrupt
(RINT).
1 Interrupt is enabled. A receive DMA error interrupt generates a McASP receive interrupt (RINT).
2 RCKFAIL Receive clock failure interrupt enable bit.
0 Interrupt is disabled. A receive clock failure interrupt does not generate a McASP receive interrupt
(RINT).
1 Interrupt is enabled. A receive clock failure interrupt generates a McASP receive interrupt (RINT).
1 RSYNCERR Unexpected receive frame sync interrupt enable bit.
0 Interrupt is disabled. An unexpected receive frame sync interrupt does not generate a McASP receive
interrupt (RINT).
1 Interrupt is enabled. An unexpected receive frame sync interrupt generates a McASP receive interrupt
(RINT).
0 ROVRN Receiver overrun interrupt enable bit.
0 Interrupt is disabled. A receiver overrun interrupt does not generate a McASP receive interrupt (RINT).
1 Interrupt is enabled. A receiver overrun interrupt generates a McASP receive interrupt (RINT).
3856
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English