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I2C Registers
21.4.1.16 I2C_BUF Register (offset = 94h) [reset = 0h]
I2C_BUF is shown in Figure 21-31 and described in Table 21-24.
This read/write register enables DMA transfers and allows the configuration of FIFO thresholds for the
FIFO management (see the FIFO Management subsection).
Figure 21-31. I2C_BUF Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
RDMA_EN RXFIFO_CLR RXTRSH
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
XDMA_EN TXFIFO_CLR TXTRSH
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-24. I2C_BUF Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15 RDMA_EN R/W 0h Receive DMA channel enable.
When this bit is set to 1, the receive DMA channel is enabled and
the receive data ready status bit (I2C_IRQSTATUS_RAW: RRDY) is
forced to 0 by the core.
Value after reset is low.
0x0 = Receive DMA channel disabled
0x1 = Receive DMA channel enabled
14 RXFIFO_CLR R/W 0h Receive FIFO clear.
When set, receive FIFO is cleared (hardware reset for RX FIFO
generated).
This bit is automatically reset by the hardware.
During reads, it always returns 0.
Value after reset is low.
0x0 = Normal mode
0x1 = Rx FIFO is reset
13-8 RXTRSH R/W 0h Threshold value for FIFO buffer in RX mode.
The receive threshold value is used to specify the trigger level for
data receive transfers.
The value is specified from the Interface/OCP point of view.
Value after reset is 00h.
For the FIFO management description, see the FIFO Management
subsection.
Note
1: programmed threshold cannot exceed the actual depth of the
FIFO.
Note
2: the threshold must not be changed while a transfer is in progress
(after STT was configured or after the module was addressed as a
slave).
0x0 = Receive Threshold value = 1
0x1 = Receive Threshold value = 2
0x3F = Receive Threshold value = 64
3745
SPRUH73H–October 2011–Revised April 2013 I2C
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