Ethernet Subsystem Registers
www.ti.com
14.5.9.18 C0_RX_STAT Register (offset = 44h) [reset = 0h]
C0_RX_STAT is shown in Figure 14-214 and described in Table 14-232.
SUBSYSTEM CORE 0 RX INTERRUPT MASKED INT STATUS REGISTER
Figure 14-214. C0_RX_STAT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
C0_RX_STAT
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-232. C0_RX_STAT Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7-0 C0_RX_STAT R 0h Core 0 Receive Masked Interrupt Status - Each bit in this read only
register corresponds to the bit in the Rx interrupt that is enabled and
generating an interrupt on C0_RX_PULSE.
1456
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
