Interrupt Controller Registers
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6.5 Interrupt Controller Registers
NOTE: FIQ is not available on general-purpose (GP) devices.
6.5.1 INTC Registers
Table 6-3 lists the memory-mapped registers for the INTC. All register offset addresses not listed in
Table 6-3 should be considered as reserved locations and the register contents should not be modified.
Table 6-3. INTC REGISTERS
Offset Acronym Register Name Section
0h INTC_REVISION Section 6.5.1.1
10h INTC_SYSCONFIG Section 6.5.1.2
14h INTC_SYSSTATUS Section 6.5.1.3
40h INTC_SIR_IRQ Section 6.5.1.4
44h INTC_SIR_FIQ Section 6.5.1.5
48h INTC_CONTROL Section 6.5.1.6
4Ch INTC_PROTECTION Section 6.5.1.7
50h INTC_IDLE Section 6.5.1.8
60h INTC_IRQ_PRIORITY Section 6.5.1.9
64h INTC_FIQ_PRIORITY Section 6.5.1.10
68h INTC_THRESHOLD Section 6.5.1.11
80h INTC_ITR0 Section 6.5.1.12
84h INTC_MIR0 Section 6.5.1.13
88h INTC_MIR_CLEAR0 Section 6.5.1.14
8Ch INTC_MIR_SET0 Section 6.5.1.15
90h INTC_ISR_SET0 Section 6.5.1.16
94h INTC_ISR_CLEAR0 Section 6.5.1.17
98h INTC_PENDING_IRQ0 Section 6.5.1.18
9Ch INTC_PENDING_FIQ0 Section 6.5.1.19
A0h INTC_ITR1 Section 6.5.1.20
A4h INTC_MIR1 Section 6.5.1.21
A8h INTC_MIR_CLEAR1 Section 6.5.1.22
ACh INTC_MIR_SET1 Section 6.5.1.23
B0h INTC_ISR_SET1 Section 6.5.1.24
B4h INTC_ISR_CLEAR1 Section 6.5.1.25
B8h INTC_PENDING_IRQ1 Section 6.5.1.26
BCh INTC_PENDING_FIQ1 Section 6.5.1.27
C0h INTC_ITR2 Section 6.5.1.28
C4h INTC_MIR2 Section 6.5.1.29
C8h INTC_MIR_CLEAR2 Section 6.5.1.30
CCh INTC_MIR_SET2 Section 6.5.1.31
D0h INTC_ISR_SET2 Section 6.5.1.32
D4h INTC_ISR_CLEAR2 Section 6.5.1.33
D8h INTC_PENDING_IRQ2 Section 6.5.1.34
DCh INTC_PENDING_FIQ2 Section 6.5.1.35
E0h INTC_ITR3 Section 6.5.1.36
E4h INTC_MIR3 Section 6.5.1.37
E8h INTC_MIR_CLEAR3 Section 6.5.1.38
ECh INTC_MIR_SET3 Section 6.5.1.39
204
Interrupts SPRUH73H–October 2011–Revised April 2013
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