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McASP Registers
22.4.1.38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time
slot). Each of the six 32-bit registers (Figure 22-76) can store 192 bits of channel status data for a
complete block of transmission. The DIT reuses the same data for the next block. It is your responsibility
to update the register file in time, if a different set of data need to be sent.
Figure 22-76. DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
31 0
DITCSRA[n]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
22.4.1.39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
The DIT right channel status registers (DITCSRB) provide the status of each right channel (odd TDM time
slot). Each of the six 32-bit registers (Figure 22-77) can store 192 bits of channel status data for a
complete block of transmission. The DIT reuses the same data for the next block. It is your responsibility
to update the register file in time, if a different set of data need to be sent.
Figure 22-77. DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
31 0
DITCSRB[n]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
22.4.1.40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
The DIT left channel user data registers (DITUDRA) provides the user data of each left channel (even
TDM time slot). Each of the six 32-bit registers (Figure 22-78) can store 192 bits of user data for a
complete block of transmission. The DIT reuses the same data for the next block. It is your responsibility
to update the register in time, if a different set of data need to be sent.
Figure 22-78. DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
31 0
DITUDRA[n]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
22.4.1.41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
The DIT right channel user data registers (DITUDRB) provides the user data of each right channel (odd
TDM time slot). Each of the six 32-bit registers (Figure 22-79) can store 192 bits of user data for a
complete block of transmission. The DIT reuses the same data for the next block. It is your responsibility
to update the register in time, if a different set of data need to be sent.
Figure 22-79. DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
31 0
DITUDRB[n]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
3875
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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