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EMIF
7.3.5.30 RDWR_LVL_RMP_WIN Register (offset = D4h) [reset = 0h]
Read-Write Leveling Ramp Window Register
Read-Write Leveling Ramp Window Register is shown in Figure 7-120 and described in Table 7-140.
Figure 7-120. Read-Write Leveling Ramp Window Register
31 30 29 28 27 26 25 24
Reserved
R-
23 22 21 20 19 18 17 16
Reserved
R-
15 14 13 12 11 10 9 8
Reserved REG_RDWRLVLINC_RMP_WIN
R- R-
7 6 5 4 3 2 1 0
REG_RDWRLVLINC_RMP_WIN
R-
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-140. Read-Write Leveling Ramp Window Register Field Descriptions
Bit Field Type Reset Description
31-13 Reserved R
Reserved.
12-0 REG_RDWRLVLINC_RM R Incremental leveling ramp window in number of refresh periods.
P_WIN The value programmed is minus one the required value.
Refresh period is defined by reg_refresh_rate in SDRAM Refresh
Control register.
455
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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