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CONTROL_MODULE Registers
9.3.53 ddr_io_ctrl Register (offset = E04h) [reset = 0h]
ddr_io_ctrl is shown in Figure 9-56 and described in Table 9-63.
Figure 9-56. ddr_io_ctrl Register
31 30 29 28 27 26 25 24
ddr3_rst_def_val ddr_wuclk_disable Reserved mddr_sel Reserved
R/W-0h R/W-0h R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved
R/W-0h
15 14 13 12 11 10 9 8
Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-63. ddr_io_ctrl Register Field Descriptions
Bit Field Type Reset Description
31 ddr3_rst_def_val R/W 0h DDR3 reset default value
30 ddr_wuclk_disable R/W 0h Disables the slow clock to WUCLKIN and ISOCLKIN of DDR emif
SS and IOs (required for proper initialization, after which clock could
be shut off).
0 = free running SLOW (32k) clock
1 = clock is synchronously gated
29 Reserved R 0h
28 mddr_sel R/W 0h 0: IOs set for DDR2/DDR3 (STL mode)
1: IOs set for mDDR (CMOS mode)
27-0 Reserved R/W 0h
817
SPRUH73H–October 2011–Revised April 2013 Control Module
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