www.ti.com
USB Registers
16.5.1.2 SYSCONFIG Register (offset = 10h) [reset = 28h]
SYSCONFIG is shown in Figure 16-23 and described in Table 16-31.
Figure 16-23. SYSCONFIG Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved USB0_OCP_EN_N PHY0_UTMI_EN_N USB1_OCP_EN_N PHY1_UTMI_EN_N
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved STANDBY_MODE IDLEMODE FREEEMU SOFT_RESET
R/W-2h R/W-2h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-31. SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
11 USB0_OCP_EN_N R/W 0h Active low clock enable for usb0_ocp_clk
0 = enable
1 = disable
10 PHY0_UTMI_EN_N R/W 0h Active low clock enable for phy0_utmi_clk
0 = enable
1 = disable
9 USB1_OCP_EN_N R/W 0h Active low clock enable for usb1_ocp_clk
0 = enable
1 = disable
8 PHY1_UTMI_EN_N R/W 0h Active low clock enable for phy1_utmi_clk
0 = enable
1 = disable
5-4 STANDBY_MODE R/W 2h Configuration of the local initiator state management mode.
0 = force-standby mode.
1 = no-standby mode.
2 = smart-standby mode.
3 = Reserved.
3-2 IDLEMODE R/W 2h Configuration of the local target state management mode.
0 = force-idle mode.
1 = no-idle mode.
2 = smart-idle mode.
3 = smart-idle with wakeup.
1 FREEEMU R/W 0h Sensitivity to emulation (debug) suspend input signal.
0 = sensitive to emulation suspend
1 = NOT sensitive to emulation suspend
0 SOFT_RESET R/W 0h Software reset of USBSS, USB0, and USB1 modules
Write 0 = No action.
Write 1 = Initiate software reset.
Read 0 = Reset done, no action.
Read 1 = Reset ongoing.
1763
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
