GPMC
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7.1.5.32 GPMC_BCH_RESULT3_i
Figure 7-82. GPMC_BCH_RESULT3_i
31 0
BCH_RESULT3_i
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-86. GPMC_BCH_RESULT3_i Field Descriptions
Bit Field Value Description
31-0 BCH_RESULT3_i 0-FFFF FFFFh BCH ECC result, bits 96 to 127
7.1.5.33 GPMC_BCH_SWDATA
This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND
flash interface.
Figure 7-83. GPMC_BCH_SWDATA
31 16
Reserved
R-0
15 0
BCH_DATA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-87. GPMC_BCH_SWDATA Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15-0 BCH_DATA 0-FFFFh Data to be included in the BCH calculation. Only bits 0 to 7 are taken into account, if
the calculator is configured to use 8 bits data (GPMC_ECC_CONFIG[7] ECC16B =
0).
7.1.5.34 GPMC_BCH_RESULT4_i
Figure 7-84. GPMC_BCH_RESULT4_i
31 0
BCH_RESULT4_i
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-88. GPMC_BCH_RESULT4_i Field Descriptions
Bit Field Value Description
31-0 BCH_RESULT4_i 0-FFFF FFFFh BCH ECC result, bits 128 to 159
396
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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