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7.3.5.17 INT_CFG_VAL_2 Register (offset = 5Ch) [reset = 0h]
Interface Configuration Value 2 Register
Interface Configuration Value 2 Register is shown in Figure 7-107 and described in Table 7-127.
Figure 7-107. Interface Configuration Value 2 Register
31 30 29 28 27 26 25 24
Reserved
R-0
23 22 21 20 19 18 17 16
REG_RREG_FIFO_DEPTH
R-2
15 14 13 12 11 10 9 8
REG_RSD_FIFO_DEPTH
R-16
7 6 5 4 3 2 1 0
REG_RCMD_FIFO_DEPTH
R-16
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-127. Interface Configuration Value 2 Register Field Descriptions
Bit Field Type Reset Description
31-24 Reserved R 0
Reserved for future use.
23-16 REG_RREG_FIFO_DEPT R 0x2
Register Read Data FIFO depth for a particular configuration.
H
15-8 REG_RSD_FIFO_DEPTH R 0x16
SDRAM Read Data FIFO depth for a particular configuration.
7-0 REG_RCMD_FIFO_DEPT R 0x16
Read Command FIFO depth for a particular configuration.
H
442
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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