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Ethernet Subsystem Registers
14.5.1.8 TBLW0 Register (offset = 3Ch) [reset = 0h]
TBLW0 is shown in Figure 14-22 and described in Table 14-32.
ADDRESS LOOKUP ENGINE TABLE WORD 0 REGISTER
Figure 14-22. TBLW0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENTRY31_0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-32. TBLW0 Register Field Descriptions
Bit Field Type Reset Description
31-0 ENTRY31_0 R/W 0h Table entry bits
31:0
1249
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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