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Touchscreen Controller Registers
12.5.1.55 FIFO1THRESHOLD Register (offset = F4h) [reset = 0h]
FIFO1THRESHOLD is shown in Figure 12-59 and described in Table 12-59.
FIFO1 Threshold trigger@TSC_ADC_SS_FIFO1 Threshold Level Register
Figure 12-59. FIFO1THRESHOLD Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved FIFO0_threshold_Level
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-59. FIFO1THRESHOLD Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5-0 FIFO0_threshold_Level R/W 0h
Program the desired FIFO0 data sample level to reach before
generating interrupt to CPU (program to value minus 1)
1093
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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