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EDMA3 Registers
11.4.1.2.7 Error Evaluation Register (EEVAL)
The EDMA3CC error interrupt is asserted whenever an error bit is set in any of the error registers
(EMR/EMRH, QEMR, and CCERR). For subsequent error bits that get set, the EDMA3CC error interrupt
is reasserted only when transitioning from an “all the error bits cleared” to “at least one error bit is set”.
Alternatively, a CPU write of 1 to the EVAL bit in the error evaluation register (EEVAL) results in
reasserting the EDMA3CC error interrupt, if there are any outstanding error bits set due to subsequent
error conditions. Writes of 0 have no effect.
The EEVAL is shown in Figure 11-58 and described in Table 11-43.
Figure 11-58. Error Evaluation Register (EEVAL)
31 16
Reserved
R-0
15 2 1 0
Reserved Rsvd EVAL
R-0 R/W-0 W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 11-43. Error Evaluation Register (EEVAL) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
1 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0 EVAL Error interrupt evaluate.
0 No effect.
1 EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers
(EMR/EMRH, QEMR, or CCERR).
957
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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