www.ti.com
Ethernet Subsystem Registers
14.5.6.32 P1_RX_DSCP_PRI_MAP5 Register (offset = 144h) [reset = 0h]
P1_RX_DSCP_PRI_MAP5 is shown in Figure 14-152 and described in Table 14-167.
CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5
Figure 14-152. P1_RX_DSCP_PRI_MAP5 Register
31 30 29 28 27 26 25 24
Reserved PRI47 Reserved PRI46
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved PRI45 Reserved PRI44
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved PRI43 Reserved PRI42
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved PRI41 Reserved PRI40
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-167. P1_RX_DSCP_PRI_MAP5 Register Field Descriptions
Bit Field Type Reset Description
30-28 PRI47 R/W 0h Priority
47 - A packet TOS of 0d47 is mapped to this received packet
priority.
26-24 PRI46 R/W 0h Priority
46 - A packet TOS of 0d46 is mapped to this received packet
priority.
22-20 PRI45 R/W 0h Priority
45 - A packet TOS of 0d45 is mapped to this received packet
priority.
18-16 PRI44 R/W 0h Priority
44 - A packet TOS of 0d44 is mapped to this received packet
priority.
14-12 PRI43 R/W 0h Priority
43 - A packet TOS of 0d43 is mapped to this received packet
priority.
10-8 PRI42 R/W 0h Priority
42 - A packet TOS of 0d42 is mapped to this received packet
priority.
6-4 PRI41 R/W 0h Priority
41 - A packet TOS of 0d41 is mapped to this received packet
priority.
2-0 PRI40 R/W 0h Priority
40 - A packet TOS of 0d40 is mapped to this received packet
priority.
1389
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
