McASP Registers
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22.4.1.8 Pin Data Clear Register (PDCLR)
The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only.
Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function)
and PDIR = 1 (output), drives a logic low on the pin. PDCLR is useful for a multitasking system because it
allows you to clear to a logic low only the desired pin(s) within a system without affecting other I/O pins
controlled by the same McASP. The PDCLR is shown in Figure 22-46 and described in Table 22-19.
CAUTION
Writing to Reserved Bits
Writing a value other than 0 to reserved bits in this register may cause improper
device operation.
Figure 22-46. Pin Data Clear Register (PDCLR)
31 30 29 28 27 26 25 24
AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
23 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved AXR5 AXR4 AXR3 AXR2 AXR1 AXR0
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3840
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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