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McASP Registers
Table 22-18. Pin Data Set Register (PDSET) Field Descriptions
Bit Field Value Description
31 AFSR Allows the corresponding AFSR bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[31] bit is set to 1.
30 AHCLKR Allows the corresponding AHCLKR bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[30] bit is set to 1.
29 ACLKR Allows the corresponding ACLKR bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[29] bit is set to 1.
28 AFSX Allows the corresponding AFSX bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[28] bit is set to 1.
27 AHCLKX Allows the corresponding AHCLKX bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[27] bit is set to 1.
26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[26] bit is set to 1.
25 AMUTE Allows the corresponding AMUTE bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[25] bit is set to 1.
24-6 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
5-0 AXR[5-0] Allows the corresponding AXR[n] bit in PDOUT to be set to a logic high without affecting other I/O pins
controlled by the same port.
0 No effect.
1 PDOUT[n] bit is set to 1.
3839
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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