Multimedia Card Registers
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18.5.1.21 SD_ISE Register (offset = 238h) [reset = 0h]
SD_ISE is shown in Figure 18-57 and described in Table 18-40.
This register allows you to enable/disable the module to set status bits, on an event-by-event basis.
SD_ISE[31:16] = Error Interrupt Signal Enable. SD_ISE[15:0] = Normal Interrupt Signal Enable.
Figure 18-57. SD_ISE Register
31 30 29 28 27 26 25 24
Reserved BADA_SIGEN CERR_SIGEN Reserved ADMA_SIGEN ACE_SIGEN
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved DEB_SIGEN DCRC_SIGEN DTO_SIGEN CIE_SIGEN CEB_SIGEN CCRC_SIGEN CTO_SIGEN
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
NULL Reserved BSR_SIGEN OBI_SIGEN CIRQ_SIGEN
R-0h R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CREM_SIGEN CINS_SIGEN BRR_SIGEN BWR_SIGEN DMA_SIGEN BGE_SIGEN TC_SIGEN CC_SIGEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-40. SD_ISE Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29 BADA_SIGEN R/W 0h
Bad access to data space interrupt enable
0x0 = Masked
0x1 = Enabled
28 CERR_SIGEN R/W 0h
Card error interrupt signal status enable
0x0 = Masked
0x1 = Enabled
27-26 Reserved R 0h
25 ADMA_SIGEN R/W 0h
ADMA error signal status enable
0x0 = Masked
0x1 = Enabled
24 ACE_SIGEN R/W 0h
Auto CMD12 error signal status enable
0x0 = Masked
0x1 = Enabled
23 Reserved R 0h
22 DEB_SIGEN R/W 0h
Data end bit error signal status enable
0x0 = Masked
0x1 = Enabled
21 DCRC_SIGEN R/W 0h
Data CRC error signal status enable
0x0 = Masked
0x1 = Enabled
20 DTO_SIGEN R/W 0h
Data timeout error signal status enable
0x0 = Masked. The host controller provides the clock to the card until
the card sends the data or the transfer is aborted.
0x1 = Enabled
19 CIE_SIGEN R/W 0h
Command index error signal status enable
0x0 = Masked
0x1 = Enabled
3432
Multimedia Card (MMC) SPRUH73H–October 2011–Revised April 2013
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