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Ethernet Subsystem Registers
14.5.8.3 SOFT_RESET Register (offset = 8h) [reset = 0h]
SOFT_RESET is shown in Figure 14-186 and described in Table 14-203.
SOFT RESET REGISTER
Figure 14-186. SOFT_RESET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SOF
T_R
ESE
T
R/
W-
0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-203. SOFT_RESET Register Field Descriptions
Bit Field Type Reset Description
0 SOFT_RESET R/W-0 0 Software reset - Writing a one to this bit causes the 3G logic to be
reset.
After writing a one to this bit, it may be polled to determine if the
reset has occurred.
If a one is read, the reset has not yet occurred.
If a zero is read then reset has occurred.
1427
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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