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7.3.5.21 PERF_CNT_SEL Register (offset = 8Ch) [reset = 0h]
PERF_CNT_SEL is shown in Figure 7-111 and described in Table 7-131.
Figure 7-111. PERF_CNT_SEL Register
31 30 29 28 27 26 25 24
reg_mconnid2
R/W-0h
23 22 21 20 19 18 17 16
Reserved reg_region_sel2
R-0h R/W-0h
15 14 13 12 11 10 9 8
reg_mconnid1
R/W-0h
7 6 5 4 3 2 1 0
Reserved reg_region_sel1
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-131. PERF_CNT_SEL Register Field Descriptions
Bit Field Type Reset Description
31-24 reg_mconnid2 R/W 0h
MConnID for Performance Counter 2 register.
23-18 Reserved R 0h
17-16 reg_region_sel2 R/W 0h
MAddrSpace for Performance Counter 2 register.
15-8 reg_mconnid1 R/W 0h
MConnID for Performance Counter 1 register.
7-2 Reserved R 0h
1-0 reg_region_sel1 R/W 0h
MAddrSpace for Performance Counter 1 register.
446
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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