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Power, Reset, and Clock Management
8.1.12.2.4 CM_WKUP_L4WKUP_CLKCTRL Register (offset = Ch) [reset = 2h]
CM_WKUP_L4WKUP_CLKCTRL is shown in Figure 8-87 and described in Table 8-95.
This register manages the L4WKUP clocks.
Figure 8-87. CM_WKUP_L4WKUP_CLKCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-95. CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions
Bit Field Type Reset Description
31-19 Reserved R 0h
18 Reserved R 0h
17-16 IDLEST R 0h
Module idle status.
0x0 = Func : Module is fully functional, including OCP
0x1 = Trans : Module is performing transition: wakeup, or sleep, or
sleep abortion
0x2 = Idle : Module is in Idle mode (only OCP part). It is functional if
using separate functional clock
0x3 = Disable : Module is disabled and cannot be accessed
15-2 Reserved R 0h
1-0 MODULEMODE R 2h
Control the way mandatory clocks are managed.
619
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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