UART Registers
www.ti.com
19.5.1.48 Transmit FIFO Level (TXFIFO_LVL) Register
The Transmit FIFO Level register (TXFIFO_LVL) is shown in Figure 19-81 and described in Table 19-80.
Figure 19-81. TXFIFO_LVL Register
31 8 7 0
Reserved TXFIFO_LVL
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-80. TXFIFO_LVL Register Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved.
7-0 TXFIFO_LVL 0 Level of the TX FIFO
3544
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
