Mailbox
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17.1.3.7 16-Bit Register Access
17.1.3.7.1 Description
So that 16-bit processors can access the mailbox module, the module allows 16-bit register read and write
access, with restrictions for the MAILBOX_MESSAGE_m registers. The 16-bit half-words are organized in
little endian fashion; that is, the least-significant 16 bits are at the low address and the most-significant 16
bits are at the high address (low address + 0x02). All mailbox module registers can be read or written to
directly using individual 16-bit accesses with no restriction on interleaving, except the
MAILBOX_MESSAGE_m registers, which must always be accessed by either single 32-bit accesses or
two consecutive 16-bit accesses.
CAUTION
When using 16-bit accesses to the MAILBOX_MESSAGE_m registers, the
order of access must be the least-significant half-word first (low address) and
the most-significant half-word last (high address). This requirement is because
of the update operation by the message FIFO of the
MAILBOX_MSGSTATUS_m registers. The update of the FIFO queue contents
and the associated status registers and possible interrupt generation occurs
only when the most-significant 16 bits of a MAILBOX_MESSAGE_m are
accessed.
17.1.4 Programming Guide
17.1.4.1 Low-level Programming Models
This section covers the low-level hardware programming sequences for configuration and usage of the
mailbox module.
17.1.4.1.1 Global Initialization
17.1.4.1.1.1 Surrounding Modules Global Initialization
This section identifies the requirements of initializing the surrounding modules when the mailbox module is
to be used for the first time after a device reset. This initialization of surrounding modules is based on the
integration of the mailbox.
See Section 17.1.2 for further information.
Table 17-6. Global Initialization of Surrounding Modules for System Mailbox
Surrounding Modules Comments
PRCM Mailbox functional/interface clock must be enabled.
Interrupt Controllers Cortex-A8 MPU interrupt controller must be configured to enable
the interrupt request generation to the Cortex-A8 MPU.
3242
Interprocessor Communication SPRUH73H–October 2011–Revised April 2013
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